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| 74ALVC162601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26 Series Resistors in the B-Port Outputs September 2001 Revised October 2001 74ALVC162601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26 Series Resistors in the B-Port Outputs General Description The 74ALVC162601, 18-bit universal bus transceiver, combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH-toLOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. Output-enable OEAB is active-LOW. When OEAB is HIGH, the outputs are in the HIGH-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA and CLKENBA. The 74ALVC162601 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O compatibility up to 3.6V. The 74ALVC162601 is also designed with 26 series resistors in the B-Port outputs. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. Features I 1.65V-3.6V VCC supply operation I 3.6V tolerant inputs and outputs I 26 series resistors in B-Port outputs I tPD (A to B) 4.3 ns max for 3.0V to 3.6V VCC 5.1 ns max for 2.3V to 2.7V VCC 9.2 ns max for 1.65V to 1.95V VCC I Power-down high impedance inputs and outputs I Supports live insertion/withdrawal (Note 1) I Uses patented noise/EMI reduction circuitry I Latchup conforms to JEDEC JED78 I ESD performance: Human body model > 2000V Machine model >200V Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number 74ALVC162601T Package Number MTD56 Package Description 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. (c) 2001 Fairchild Semiconductor Corporation DS500676 www.fairchildsemi.com 74ALVC162601 Pin Descriptions Pin Names OEAB, OEBA LEAB, LEBA CLKAB, CLKBA CLKENAB, CLKENBA A1-A18 B1-B18 Description Output Enable Inputs (Active LOW) Latch Enable Inputs Clock Inputs Clock Enable Inputs Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs (Note 2) Outputs An X L H X X L H X X Bn Z L H B0 (Note 3) B0 (Note 3) L H B0 (Note 3) B0 (Note 4) Connection Diagram Function Table Inputs CLKENAB OEAB LEAB CLKAB X X X H H L L L L H L L L L L L L L X H H L L L L L L X X X X X L H Logic Diagram H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance Note 2: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, CLKBA, and CLKENBA. Note 3: Output level before the indicated steady-state input conditions were established. Note 4: Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. www.fairchildsemi.com 2 74ALVC162601 Absolute Maximum Ratings(Note 5) Supply Voltage (VCC) DC Input Voltage (VI) Output Voltage (VO) (Note 6) DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V DC Output Source/Sink Current (IOH/IOL) DC VCC or GND Current per Supply Pin (ICC or GND) Storage Temperature Range (TSTG) -0.5V to +4.6V -0.5V to 4.6V -0.5V to VCC +0.5V -50 mA -50 mA 50 mA 100 mA -65C to +150C Recommended Operating Conditions (Note 7) Power Supply Operating Input Voltage Output Voltage (VO) Free Air Operating Temperature (TA) Minimum Input Edge Rate (t/V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V Note 5: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 6: IO Absolute Maximum Rating must be observed. Note 7: Floating or unused control inputs must be held HIGH or LOW. 1.65V to 3.6V 0V to VCC 0V to VCC -40C to +85C DC Electrical Characteristics Symbol VIH Parameter HIGH Level Input Voltage Conditions VCC (V) 1.65 - 1.95 2.3 - 2.7 2.7 - 3.6 VIL LOW Level Input Voltage 1.65 - 1.95 2.3 - 2.7 2.7 - 3.6 VOH HIGH Level Output Voltage A Outputs IOH = -100 A IOH = -4 mA IOH = -6 mA IOH = -12 mA 1.65 - 3.6 1.65 2.3 2.3 2.7 3.0 IOH = -24 mA HIGH Level Output Voltage B Outputs IOH = -100 A IOH = -2 mA IOH = -4 mA IOH = -6 mA IOH = -8 mA IOH = -12 mA VOL LOW Level Output Voltage A Outputs IOL = 100 A IOL = 4 mA IOL = 6 mA IOL = 12 mA IOL = 24 mA LOW Level Output Voltage B Outputs IOL = 100 A IOL = 2 mA IOL = 4 mA IOL = 6 mA IOL = 8 mA IOL = 12 mA 3.0 1.65 - 3.6 1.65 2.3 2.3 3.0 2.7 3.0 1.65 - 3.6 1.65 2.3 2.3 2.7 3.0 1.65 - 3.6 1.65 2.3 2.3 3.0 2.7 3.0 VCC - 0.2 1.2 2.0 1.7 2.2 2.4 2 VCC - 0.2 1.2 1.9 1.7 2.4 2 2 0.2 0.45 0.4 0.7 0.4 0.55 0.2 0.45 0.4 0.55 0.55 0.6 0.8 V V Min 0.65 x VCC 1.7 2.0 0.35 x VCC 0.7 0.8 V V Max Units 3 www.fairchildsemi.com 74ALVC162601 DC Electrical Characteristics Symbol IOH Parameter High Level Output Current A Outputs (Continued) VCC (V) 1.65 2.3 2.7 3.0 -4 -12 -12 -24 -2 -6 -8 -12 4 12 12 24 2 6 8 12 5.0 10 10 40 750 A A mA A A mA mA Conditions Min Max Units High Level Output Current B Outputs 1.65 2.3 2.7 3.0 IOL Low Level Output Current A Outputs 1.65 2.3 2.7 3 Low Level Output Current B Outputs 1.65 2.3 2.7 3.0 II IOZ IOFF ICC ICC Input Leakage Current 3-STATE Output Leakage Power Off Leakage Current Quiescent Supply Current Increase in ICC per Input 0 VI 3.6V 0 VO 3.6V, VI = VIH or VIL 0V (VI, VO) 3.6V VI = VCC or GND, IO = 0 VIH = VCC - 0.6V 1.65 - 3.6 1.65 - 3.6 0 3.6 2.7 - 3.6 AC Electrical Characteristics TA = -40C to +85C, RL = 500 Symbol Parameter CL = 50 pF VCC = 3.3V 0.3V Min fMAX tPHL, tPLH Maximum Clock Frequency Propagation Delay 1.3 A to B ns Propagation Delay 1.3 B to A tPHL, tPLH Propagation Delay 1.3 Clock to A ns Propagation Delay 1.3 Clock to B tPHL, tPLH Propagation Delay 1.3 LEBA to A ns Propagation Delay 1.3 LEAB to B tPZL, tPZH Output Enable Time 1.3 OEBA to A ns Output Enable Time 1.3 OEAB to B 4.8 1.5 6.4 1.0 5.9 1.5 9.8 4.3 1.5 5.4 1.0 4.9 1.5 9.8 4.9 1.5 6.3 1.0 5.8 1.5 9.8 4.0 1.5 4.9 1.0 4.4 1.5 8.8 4.9 1.5 6.0 1.0 5.5 1.5 9.8 4.0 1.5 4.9 1.0 4.4 1.5 8.8 3.4 1.5 4.0 1 3.5 1.5 7.0 4.3 1.5 5.1 1 4.6 1.5 9.2 250 Max VCC = 2.7V Min 200 Max CL = 30 pF VCC = 2.5 0.2V Min 200 Max VCC = 1.8V 0.15V Min 125 Max MHz Units www.fairchildsemi.com 4 74ALVC162601 AC Electrical Characteristics Symbol Parameter (Continued) TA = -40C to +85C, RL = 500 CL = 50 pF CL = 30 pF VCC = 2.5 0.2V Min 1.0 Max 4.2 VCC = 1.8V 0.15V Min 1.5 Max 7.6 ns Units VCC = 3.3V 0.3V Min Max 4.2 VCC = 2.7V Min 1.5 Max 4.7 tPLZ, tPHZ Output Disable Time 1.3 OEBA to A Output Disable Time 1.3 OEAB to B 4.8 1.5 5.4 1.0 4.9 1.5 8.8 TA = -40C to +85C, RL = 500 Symbol Parameter CL = 50 pF VCC = 3.3V 0.3V Min tS tH tW Setup Time Hold Time Pulse Width 1.5 1.0 1.5 Max VCC = 2.7V Min 1.5 1.0 1.5 Max CL = 30 pF VCC = 2.5 0.2V Min 1.5 1.0 1.5 Max VCC = 1.8V 0.15V Min 2.5 1.0 4.0 Max ns ns ns Units Capacitance Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter Conditions VI = 0V or VCC VI = 0V or VCC Outputs Enabled f = 10 MHz, CL = 0 pF TA = +25C VCC 3.3 3.3 3.3 2.5 Typical 6 7 20 20 Units pF pF pF 5 www.fairchildsemi.com 74ALVC162601 AC Loading and Waveforms Table 1: Values for Figure 1 TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ SWITCH Open VL GND FIGURE 1. AC Test Circuit Table 2: Variable Matrix ( Input Charactertistics: f = 1MHz; tr=tf=2ns; Z0= 50 ) Symbol Vmi Vmo VX VY VL VCC 3.3V 0.3V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 6V 2.7V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 6V 2.5V 0.2V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V VCC*2 1.8V 0.15V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V VCC*2 FIGURE 2. Waveform for Inverting and Non-inverting Functions FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 5. Propagation Delay, Pulse Width and trec Waveforms FIGURE 6. Setup Time, Hold Time and Recovery Time for Low Voltage Logic www.fairchildsemi.com 6 74ALVC162601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26 Series Resistors in the B-Port Outputs Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com |
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